Scaling techniques for increasing the integration density of a semiconductor device include a multi-gate transistor in which a fin- or nanowire-shaped multi-channel active pattern (or a silicon body) is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.
The multi-gate transistor uses a three-dimensional channel, thus it may be scaled relatively easily. Furthermore, the multi-gate transistor may have improved current control capability without increasing the length of the gate thereof. Furthermore, a short channel effect (SCE) in which electric potential in a channel region is influenced by a drain voltage can be effectively suppressed.
As semiconductor devices are made increasingly smaller, the importance of isolation between transistors is being emphasized. A need therefore exists for improved manufacturing methods for devices in which characteristics of isolation between a plurality of transistors formed on a fin.